20 n-channel logic level enhancement mode field effect transistor preliminary features 20v , 20a , r ds(on) =40m @v gs =4.5v. super high dense cell design for extremely low r ds(on) . high power and current handling capability. to-251 & to-252 package. absolute maximum ratings (tc=25 c unless otherwise noted) parameter symbol limit unit drain-source voltage v ds v gate-source voltage v gs 12 v drain current-continuous -pulsed i d 20 a i dm 60 a drain-source diode forward current i s 20 a maximum power dissipation p d w operating and storage temperature range t j ,t stg -55 to 175 c thermal characteristics thermal resistance, junction-to-case thermal resistance, junction-to-ambient r / jc r / ja 4 50 /w c /w c ? r ds(on) =70m @v gs =2.5v. ? ced21a2/CEU21A2 @tc=25 c derate above 25 c 38 0.25 w/ c s g d ceu series to-252aa(d-pak) ced series to-251(l-pak) g g s s d d 6 1
ced21a2/CEU21A2 electrical characteristics (t c 25 c unless otherwise noted) = parameter symbol condition min typ max unit off characteristics drain-source breakdown voltage bv dss v gs =0v,i d= 250 a 20 v zero gate voltage drain current i dss v ds = 20v, v gs =0v 1 a gate-body leakage i gss v gs =12v,v ds =0v 100 na on characteristics a gate threshold voltage v gs(th) v ds =v gs ,i d =250 a 0.5 1.5 v drain-source on-state resistance r ds(on) v gs =4.5v,i d =8a 30 40 m v gs =2.5v,i d = 6.6a 55 70 m on-state drain current i d(on) v ds =5v,v gs =4.5v 20 15 a s forward transconductance fs g v ds = 10v, i d =8a dynamic characteristics b input capacitance c iss c rss c oss output capacitance reverse transfer capacitance v ds =15v, v gs =0v f=1.0mh z 511 p f 216 p f p f 73 switching characteristics b turn-on delay time rise time turn-off delay time t d(on) t r t d(off) t f v dd =10v, i d =1a v gs =4.5v, r gen =6 20 50 ns ns ns ns 12 30 50 100 10 25 total gate charge gate-source charge gate-drain charge q g q gs q gd nc nc nc c fall time 2 4 11 2.8 15 v ds =10v,i d =8a v gs =4.5v 6 3.6
parameter symbol condition min typ max unit electrical characteristics (t c =25 c unless otherwise noted) drain-source diode characteristics diode forward voltage v sd v gs =0v,is=4a 1.3 v a notes b.guaranteed by design, not subject to production testing. a.pulse test:pulse width 300 3 s, duty cycle 2%. figure 1. output characteristics figure 2. transfer characteristics figure 3. capacitance v ds , drain-to source voltage (v) v gs , gate-to-source voltage (v) v ds , drain-to-source voltage (v) c, capacitance (pf) i d , drain current (a) i d , drain current (a) [ [ 3 ced21a2/CEU21A2 figure 4. on-resistance variation with temperature t j , junction temperature( c) on-resistance(ohms) r ds(on) , r ds(on) , normalized 15 12 9 6 3 0 0.5 1 1.5 2 2.5 25 c tj=125 c -55 c 30 25 20 15 10 5 0 0 1 2 4 3 v gs = 1 .5v v gs =2v v gs =2.5v v gs =4.5,3.5,3v 6 0 5 10 15 20 ciss coss crss 0 1000 800 600 400 200 -100 -50 0 50 100 200 2.2 1.9 1.6 1.3 1.0 0.7 0.4 v gs =4.5v i d =8a 150
ced21a2/CEU21A2 with temperature figure 6. breakdown voltage variation figure 5. gate threshold variation with temperature vth, normalized gate-source threshold voltage g fs , transconductance (s) v gs , gate to source voltage (v) bv dss , normalized drain-source breakdown voltage is, source-drain current (a) figure 7. transconductance variation with drain current i ds , drain-source current (a) figure 9. gate charge qg, total gate charge (nc) figure 10. maximum safe operating area v ds , drain-source voltage (v) figure 8. body diode forward voltage variation with source current v sd , body diode forward voltage (v) tj, junction temperature ( c) tj, junction temperature ( c) i d , drain current (a) 4 1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 -50 -25 0 25 50 75 100 125 150 v d s =v gs i d =250 3 a 5 0 1 2 3 4 03 6 9 12 v ds =10v i d =8a 50 10 1.0 0.1 0.6 0.8 1.0 1.2 1.4 20 16 12 8 4 0 0 3 6912 v ds =10v 10 10 -1 10 1 0 10 1 10 -2 10 0 10 -1 10 2 10 2 t a =25 c single pulse r / ja = 50 c/w dc 10ms 10s 1s 100ms r ds (on)li mit 6 -50 -25 0 25 50 75 100 125 150 1.15 1.10 1.05 1.00 0.95 0.90 0.85 i d =250 3 a
figure 11. switching test circuit figure 12. switching waveforms ced21a2/CEU21A2 t v v t t d(on) out in on r 10% t d(off) 90% 10% 10% 50% 50% 90% t off t f 90% pulse width 5 4 inverted transient thermal impedance square wave pulse duration (sec) figure 13. normalized thermal transient impedance curve r(t),normalized effective v dd r d v v r s v g gs in gen out l 10 -4 10 -3 10 -2 10 -1 10 0 p dm t 1 t 2 1. r / jc (t)=r (t) * r / jc 2. r / jc =see datasheet 3. t jm- t c =p*r / jc (t) 4. duty cycle, d=t1/t2 10 -3 10 -2 10 -1 10 0 10 2 10 1 single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 6
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